In the manufacturing process of the integrated circuit, it is important to form a thin silicide layer on the source/drain regions of the transistors in order to reduce the resistance of the source/drain regions for maintaining high performance of the transistor and resultant circuits. The silicidation on the source/drain regions can be achieved by a simple silicidation on the source/drain regions alone or by the self-aligned silicidation on the source/drain regions and the gate regions of the transistors. It has been well known that the electrostatic discharge (ESD) robustness is a critical parameter of the product of the resultant circuits. However, it is severely impaired by the silicidation. Therefore, several methods have been developed to prevent the electrostatic discharge protection of the transistor from getting worsen due to the silicidation. One method is to utilize the selective implantation of phosphorus ion or arsenic ion into the source/drain regions of the transistors for allowing the growth of a thicker oxide and preventing the silicidation on the source/drain regions. However, phosphorus ion and arsenic ion, both of which are active dopants to silicon, will significantly affect the drain engineering structure of ESD transistor that is not compatible with the design for the deep sub-micron device. Furthermore, this kind of method is only suitable for avoiding the silicidation on n-channel ESD transistors, but not simultaneously on n-channel and p-channel ESD transistors. It is the purpose of the present invention to deal with the above situation encountered by the prior art.